Espressif announces the release of the ESP32-S2 Secure Wi-Fi MCU, which is a highly integrated, low-power, 2.4 GHz Wi-Fi Microcontroller SoC supporting Wi-Fi HT40 and 43 GPIOs. Based on Xtensa® single-core 32-bit LX7 processor, ESP32-S2 can be clocked at up to 240 MHz.
ESP32-S2 is a highly integrated, low-power, 2.4 GHz Wi-Fi Microcontroller SoC supporting Wi-Fi HT40 and 43 GPIOs. Based on Xtensa® single-core 32-bit LX7 processor, it can be clocked at up to 240 MHz.
With state-of-the-art power management and RF performance, IO capabilities and security features, ESP32-S2 is an ideal choice for a wide variety of IoT or connectivity-based applications, including smart home and wearables. With an integrated 240 MHz Xtensa® core, ESP32-S2 is sufficient for building the most demanding connected devices without requiring external MCUs.
By leveraging Espressif’s mature and production-ready software development framework (ESP-IDF), ESP32-S2 achieves a balance of performance and cost, thus bringing faster and more secure IoT connectivity solutions to the market.
CPU And Memory
- Xtensa® single-core 32-bit LX7 microcontroller
- 7-stage pipeline
- Clock frequency of up to 240 MHz
- Ultra-low-power co-processor
- 320 kB SRAM, 128 kB ROM, 16 KB RTC memory
- External SPIRAM (128 MB total) support
- Up to 1 GB of external flash support
- Separate instruction and data cache
- Wi-Fi 802.11 b/g/n
- 1×1 transmit and receive
- HT40 support with data rate up to 150 Mbps
- Support for TCP/IP networking, ESP-MESH networking, TLS 1.0, 1.1 and 1.2 and other networking protocols over Wi-Fi
- Support Time-of-Flight (TOF) measurements with normal Wi-Fi packets
- 43 programmable GPIOs
- 14 capacitive touch sensing IOs
- Standard peripherals including SPI, I2C, I2S, UART, ADC/DAC and PWM
- LCD (8-bit parallel RGB/8080/6800) interface and also support for 16/24-bit parallel
- Camera interface supports 8 or 16-bit DVP image sensor, with clock frequency of up to 40 MHz
- Full speed USB OTG support
- RSA-3072-based trusted application boot
- AES256-XTS-based flash encryption to protect sensitive data at rest
- 4096-bit eFUSE memory with 2048 bits available for application
- Digital signature peripheral for secure storage of private keys and generation of RSA signatures
Engineering Samples of ESP32-S2 beta will be available in June.